The invention concerns a switching control arrangement for a multilevel convertor, in particular, but not exclusively, a chain-circuit multilevel convertor.
The chain-circuit is illustrated in FIG. 1. This includes a number (defined as N, where N will be typically 6 or more) similar `links` 10 connected in series on their AC sides to form a complete chain 12. As shown, the chain is connected to an AC power system 13 via an inductor 14. One link is shown in detail and includes four electronic switches 15 to 18. For high equipment ratings, for example 20 MVA or more, the principal component in each electronic switch may be a gate turn-off thyristor (GTO) with a reverse parallel-connected diode as shown and this will be generally assumed for reference here; the alternative use of transistors of various types is also possible, particularly at lower ratings.
The electronic switches in each link form a voltage-commutated convertor. As shown in FIG. 1, this commutates against a capacitor 19 on its DC side and the circuit is then suitable for use as a Static VAr Compensator (SVC) for the supply of positive or negative controllable reactive power (VAr) to the AC system; the general description will center around this application of the multilevel convertor, although, as mentioned later, other applications are possible within the context of the invention.
First, it is assumed that the DC capacitors are of high capacitance. For a particular link, assuming that its capacitor has a voltage V.sub.DC and ignoring any AC ripple on the capacitor for the present, the voltage on the AC side of the link in FIG. 1 may be set to values of:
______________________________________ +V.sub.DC if switches 16, 17 only are turned on 0 if switches 15, 17 (or 16, 18 only are turned on -V.sub.DC if switches 15, 18 only are turned on ______________________________________
By suitably controlling the timing of the switchings within each fundamental- frequency cycle of the AC system by way of the switching pattern generating means 11, the AC voltage V.sub.LINK of one link, as defined in FIG. 1, may then be made as in FIG. 2 (ignoring the dashed lines for the present), in which the switching times are shown as .theta., .pi.-.theta., .pi.+.theta. and 2.pi.-.theta. electrical radians within one cycle. The angle .theta. is defined as the "characteristic angle" of the link; its value will generally be different for each link.
This forms a symmetrical waveform, having a fundamental frequency and odd harmonics only. The total AC voltage V.sub.CHAIN of the chain will be the summation of the AC voltages of each link, giving a `stepped` waveform similar to that shown in FIG. 3, which is for a 6-link chain.
It will be clear from FIG. 3 that by suitable selection of the N characteristic switching angles .theta., to .theta..sub.N (for an N-link chain) the stepped waveform can be arranged to be a close approximation to a fundamental-frequency sine wave. Angles may be chosen so as to null selected harmonics (such as orders 5, 7, 11, 13, . . . ) or to give a least-error fit to a reference sine wave.
It is known to construct an analogue form of control for this or similar circuits in which a common reference sine waveform or symmetrical saw-tooth waveform is applied to a set of comparators to generate the desired gate waveforms for the switches (GTOs) in each convertor. FIG. 4A shows a possible arrangement for one link, for example link 10-1. In this, a fixed DC voltage V.sub.1 is applied to one input of a comparator 34-1A and, via an inverting amplifier 35, to one input of a second comparator 34-1B. To both second inputs of the comparators 34-1A and 34-1B is taken a common reference waveform, in this example a symmetrical triangular waveform.
Comparator 34-1B is oppositely configured at its input compared with comparator 34-1A, such that the outputs of the two comparators go logic LOW when the absolute value of the reference sawtooth voltage exceeds that of the voltage V.sub.1 --V.sub.1 applied to the comparators.
The comparators supply four coupling-isolator means 40-1A, 40-1B, 40-1C and 40-1D, which may, for example take the form of optical fibres and amplifiers, and these coupling means in turn feed the gates of switches 17, 16, 18 and 15, respectively. Coupling means 40-1B and 40-1C are fed indirectly by way of a logic circuit 33 comprising a NAND-gate 36 and two AND gates 37, 38 connected as shown. In this particular arrangement the GTOs are driven into conduction by a LOW signal on the comparator outputs, the coupling means normally then delivering a HIGH output to interface with the actual GTO gates.
By suitable choice of V.sub.1 gate, waveforms are produced which correspond to the desired rectangular link waveform V.sub.LINK shown in FIG. 2, except that all pulses are unipolar for driving the GTOs. The purpose of the logic circuit 33 is to ensure that, during those times when the link voltage is zero, the appropriate pair of GTOs (in this case, GTOs 16 and 18) is switched on to form an effective short-circuit. The respective switching angles in each cycle inherently form the required pattern (.theta..sub.1, .pi.-.theta..sub.1, .pi.+.theta..sub.1, 2.pi.-.theta..sub.1, etc.). Thus the value of the characteristic angle .theta..sub.1, for link reference 1 is determined by suitable choice of V.sub.1.
For the other links, similar comparators, logic gates and output coupling/isolator means may be used, but their fixed input voltages V.sub.2, V.sub.3, etc are chosen appropriately to produce the different characteristic angles .theta..sub.2, .theta..sub.3, etc. FIG. 4B shows the general arrangement, except that for simplicity the group of comparator and isolator means for each link is shown as a single comparator and isolator only, such as 34-1 and 40-1, respectively, and the logic circuit 33 is omitted. It should be realized, however, that the omitted components would, in practice, be included.
FIG. 4C shows a digital equivalent in which a digital look-up table 20 replaces the set of voltages V.sub.1, V.sub.2 . . . V.sub.N and contains N locations each occupied by a number corresponding to a particular threshold value. Digital comparators 30-1 to 30-N replace analogue comparators 34-1 to 34-N and their outputs are taken to the GTO gates via respective coupling/isolating means 40-1 to 40-N. The comparators are controlled by a digital clock, in the form of a digital number increasing progressively from, for example, zero to 4096 in steps of 1, then falling similarly back to zero and repeating synchronously with the AC system frequency, thereby replacing the analogue triangular reference waveform of FIG. 4A. FIG. 4C is again simplified in a similar manner to FIG. 4B and in reality contains four comparators and coupling means, and a logic circuit, for each chain link, generally as FIG. 4B.
A main control system will normally be used to move the entire switching pattern "en masse" in phase relative to the AC system voltage in response to the deviation of a measured quantity (such as fundamental-frequency current) from a desired value, in a closed loop to tend to reduce the deviation to zero. Since this is not a part of the present invention it will not be further discussed in this specification.
As described above, capacitor voltages are assumed to be ripple-free and only one switching pattern is therefore required since, while the amplitude of the waveform in FIG. 3 may naturally change with working conditions (fundamental-frequency voltage and current) the shape is not required to do so. In practice this is too simplistic, since it implies capacitors of infinite capacitance.
In a practical AC system substantial AC current will flow and this current will flow in each capacitor for parts of each cycle. Since capacitors have to be limited by physical size and cost, substantial ripple will appear on each capacitor added to its basic DC voltage. The effect on the AC voltage of one link is shown by the dashed lines in FIG. 2; the effects on the chain voltage of FIG. 3 are to replace the horizontal parts of the waveform by curved portions (not shown). There will be a substantial change in the fundamental voltage of the chain and this will be automatically compensated for by the main control system; however, if the switching pattern is unchanged there will also be large (and usually unacceptable) increases in the harmonic voltages generated by the chain (or the accuracy of the least-error fit to a sine wave, where this is selected as the criterion, will be severely impaired).
The present invention addresses the problem of harmonic corruption occurring during changing current-load conditions.